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Floorplanning
Placements
CTS
Route
ECO implementations
Pipeline planning
Timing closure(Setup/hold/TDRC)
DCD/Aging DCD
Latency/skew checks
Derates methodology(OCV/POCV/SPOCV etc)
Single bit/Multi bit
Formal verification
SSN/SSH insertion
Functional verification
Static Timing Analysis
SystemVerilog (SV) verification
Universal Verification Methodology (UVM)
VHDL (VHSIC Hardware Descriptive Language)
Full-custom
Standard Cells
Gate-arrays
FPGAs
CPLDs and Design Approach for Full-custom and Semi-custom devices