Current open positions
3+ years industry experience with following skillset
You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts. Your responsibility may include participating in cutting-edge physical design methodology and flow development.
What We're Looking For
Fill chip partition
Floor planning / Pin placement
Placement Congestion/utilization/Timing analysis)
Clock tree synthesis
click latency/Skew analysis
Inter clock balancing requirements analysis
Routing
EM/IR checks
Sign off timing analysis
Technology nodes: 3 nm/ 4nm/ 7nm expertise
Scripting languages: Pearl/Tcl/Python